View MAX5200_47755.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-2655; Rev 1; 1/03
Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in MAX
General Description
The MAX5200-MAX5203 serial input, voltage-output, 16-bit digital-to-analog converters (DACs) provide monotonic 16-bit output over temperature without any adjustments. The MAX5200/MAX5201 operate from a +5V single power supply featuring an internal reference of +2.5V and an internal gain of 2, while the MAX5202/ MAX5203 operate from a +3V or +3.3V single power supply featuring an internal reference of +1.5V and an internal gain of 2. The MAX5200-MAX5203 DAC output range is typically from 0 to VDD. The MAX5200-MAX5203 feature a hardware reset input (CLR) that, when pulled low, clears the output to zero code 0000 hex (MAX5201/MAX5203) or resets the output to midscale code 8000 hex (MAX5200/MAX5202). The 3-wire serial interface is compatible with SPITM/QSPITM/MICROWIRETM. All devices have a lowpower shutdown mode that reduces the supply current consumption to 1A. The MAX5200-MAX5203 are available in a space-saving 10-pin MAX package and are guaranteed over the extended temperature range (-40C to +105C). Refer to the MAX5204-MAX5207 data sheet for external reference versions. o Guaranteed 16-Bit Monotonic o Internal Reference o 10-Pin 5mm 3mm MAX Package o Rail-to-Rail(R) Output Amplifier o Single-Supply Operation +5V (MAX5200/MAX5201) +3V, +3.3V (MAX5202/MAX5203) o Low Power Consumption: 0.8mA o Shutdown Mode Reduces Supply Current to 1A o SPI/QSPI/MICROWIRE-Compatible 3-Wire Serial Interface o Power-On-Reset Sets Output to Midscale (MAX5200/MAX5202) Zero Scale (MAX5201/MAX5203)
Features
MAX5200-MAX5203
Applications
Low-Cost VCO/VCXO Frequency Control Industrial Process Control High-Resolution Offset Adjustment
PART MAX5200AEUB MAX5200BEUB MAX5200ACUB MAX5201AEUB MAX5201BEUB MAX5201ACUB MAX5202AEUB
CLR 1 REF AGND VDD OUT 2 3 4 5 10 DGND 9 SCLK DIN LDAC CS
Ordering Information
TEMP RANGE -40C to +105C -40C to +105C 0C to +105C -40C to +105C -40C to +105C 0C to +105C -40C to +105C -40C to +105C 0C to +105C -40C to +105C -40C to +105C 0C to +105C PIN-PACKAGE 10 MAX 10 MAX 10 MAX 10 MAX 10 MAX 10 MAX 10 MAX 10 MAX 10 MAX 10 MAX 10 MAX 10 MAX
Pin Configuration
TOP VIEW
MAX5202BEUB MAX5202ACUB MAX5203AEUB MAX5203BEUB MAX5203ACUB
MAX5200- MAX5203
8 7 6
MAX
Selector Guide appears at end of data sheet. SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in MAX MAX5200-MAX5203
ABSOLUTE MAXIMUM RATINGS
VDD to AGND, DGND ...............................................-0.3V to +6V AGND to DGND...................................................-0.3V to +0.3V REF, OUT to AGND....................................-0.3V to (VDD + 0.3V) CLR, LDAC, SCLK, DIN, CS to DGND .......-0.3V to (VDD + 0.3V) Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 10-Pin MAX (derate 5.6mW/C above +70C) ........444.4mW Operating Temperature Ranges MAX520_CUB ...................................................0C to +105C MAX520_EUB ...............................................-40C to +105C Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS--MAX5200/MAX5201
(VDD = +4.75V to +5.25V, fSCLK = 10MHz (50% duty cycle), output load = 10k in parallel with 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER STATIC PERFORMANCE (Note 1) Resolution Integral Nonlinearity (Note 2) N MAX520_AEUB INL MAX520_ACUB MAX520_BEUB MAX520_A_UB (Note 3) Differential Nonlinearity (Note 2) Offset Error Gain Error Power-Supply Rejection DYNAMIC PERFORMANCE DAC Output Range Output-Voltage Slew Rate Output Settling Time Output Noise DAC Glitch Impulse Digital Feedthrough Wake-Up Time Power-Up Time SR To 1LSB of FS, VSTEP = 0.25 x VREF to 0.75 x VREF DAC code = 8400 hex, 10kHz Major carry transition (code 7FFF hex to code 8000 hex) Code = 0000 hex; CS = VDD; LDAC = 0; SCLK, DIN = 0 or VDD From software shutdown to 90% of output code = FFFF hex, CREF = 0.1F From power applied to 90% of output code = FFFF hex (Note 2) 0 to VDD 0.6 25 175 10 10 50 10 V V/s s nV/Hz nVs nVs s ms GE PSR DNL MAX520_BEUB (0C to +105C) (Note 3) MAX520_BEUB (-40C to 0C) Inferred from measurement at 1C00 hex and FFFF hex Within DAC output range (Note 4) VDD = 5V 5%, midscale input 3 0.01 0.06 16 10 10 20 20 20 40 1 1 2 25 1 0.5 mV %FSR mV/V LSB LSB Bits SYMBOL CONDITIONS MIN TYP MAX UNITS
2
_______________________________________________________________________________________
Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in MAX
ELECTRICAL CHARACTERISTICS--MAX5200/MAX5201 (continued)
(VDD = +4.75V to +5.25V, fSCLK = 10MHz (50% duty cycle), output load = 10k in parallel with 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER INTERNAL REFERENCE VREF Output Voltage VREF Tempco DIGITAL INPUTS (DIN, SCLK, CS, CLR, LDAC) Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Input Capacitance POWER REQUIREMENTS Positive Power Supply Positive Supply Current Shutdown Supply Current TIMING CHARACTERISTICS SCLK Frequency SCLK Clock Period SCLK Pulse Width High SCLK Pulse Width Low DIN Setup Time DIN Hold Time CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time SCLK Rise to CS Fall Ignore CS Rise to SCLK Rise Ignore LDAC Pulse Width CS Rise to LDAC Low Setup SCLK Fall to CS Fall Ignore CS Pulse Width Low for Shutdown CS Pulse Width High fSCLK tCP tCH tCL tDS tDH tCSS tCSH tCS0 tCS1 tLDAC tLDACS tCSOL tCSWL tCSWH 100 40 40 40 0 40 0 10 40 40 40 10 40 100 10 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns VDD IDD ISHDN All digital inputs at 0 or VDD (Note 5) All digital inputs at 0 or VDD 4.75 0.8 1 5.25 1.5 10 V mA A VIH VIL VHYST IIN CIN Digital inputs = 0 or VDD 15 200 1 2.4 0.8 V V mV A pF TA = +25C TA = 0C to +105C TA = -40C to +105C 2.48 2.5 15 20 2.52 V ppm/C SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5200-MAX5203
_______________________________________________________________________________________
3
Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in MAX MAX5200-MAX5203
ELECTRICAL CHARACTERISTICS--MAX5202/MAX5203
(VDD = +2.7V to +3.6V, fSCLK = 10MHz (50% duty cycle), output load = 10k in parallel with 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER STATIC PERFORMANCE (Note 1) Resolution Integral Nonlinearity (Note 2) N MAX520_AEUB INL MAX520_ACUB MAX520_BEUB MAX520_A_UB (Note 3) Differential Nonlinearity (Note 2) Offset Error Gain Error Power-Supply Rejection DYNAMIC PERFORMANCE DAC Output Range Voltage-Output Slew Rate Output Settling Time Output Noise Reference Feedthrough DAC Glitch Impulse Digital Feedthrough Wake-Up Time Power-Up Time SR To 1 LSB of FS, VSTEP = 0.25 VREF to 0.75 VREF Code = 8400 hex, 10kHz Code = 0000 hex at 100kHz, VREF = 1VP-P Major carry transition (code 7FFF hex to code 8000 hex) Code = 0000 hex; CS = VDD; LDAC = 0; SCLK, DIN = 0 or VDD levels From software shutdown to 90% of output code = FFFF hex From power applied to 90% of output code = FFFF hex (Note 2) 0 to VDD 0.6 25 175 1 10 10 50 10 V V/s s nV/Hz mVP-P nVs nVs s ms GE PSR DNL MAX520_BEUB (0C to +105C) (Note 3) MAX520_BEUB (-40C to 0C) Inferred from measurement at 3800 hex and FFFF hex Within DAC output range (Note 4) VDD = 3V 10%, midscale input 3 0.01 0.06 16 10 10 20 20 20 40 1 1 2 25 1.0 0.5 mV %FSR mV/V LSB LSB Bits SYMBOL CONDITIONS MIN TYP MAX UNITS
4
_______________________________________________________________________________________
Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in MAX
ELECTRICAL CHARACTERISTICS--MAX5202/MAX5203 (continued)
(VDD = +2.7V to +3.6V, fSCLK = 10MHz (50% duty cycle), output load = 10k in parallel with 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER INTERNAL REFERENCE VREF Output Voltage VREF Tempco DIGITAL INPUTS (DIN, SCLK, CS, CLR, LDAC) Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Input Capacitance POWER REQUIREMENTS Positive Power Supply Positive Supply Current Shutdown Supply Current TIMING CHARACTERISTICS SCLK Frequency SCLK Clock Period SCLK Pulse Width High SCLK Pulse Width Low DIN Setup Time DIN Hold Time CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time SCLK Rise to CS Fall Ignore CS Rise to SCLK Rise Ignore LDAC Pulse Width CS Rise to LDAC Low Setup SCLK Fall to CS Fall Ignore CS Pulse Width Low for Shutdown CS Pulse Width High fSCLK tCP tCH tCL tDS tDH tCSS tCSH tCS0 tCS1 tLDAC tLDACS tCSOL tCSWL tCSWH 100 40 40 40 0 40 0 10 40 40 40 10 40 100 10 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns VDD IDD ISHDN All digital inputs at 0 or VDD (Note 5) All digital inputs at 0 or VDD 2.7 0.8 1 3.6 1.5 10 V mA A VIH VIL VHYST IIN CIN Digital inputs = 0 or VDD 15 200 1 2.1 0.6 V V mV A pF TA = +25C TA = 0C to +70C TA = -40C to +85C 1.46 1.5 15 20 1.54 V ppm/C SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5200-MAX5203
Note 1: Note 2: Note 3: Note 4: Note 5:
Static performance tested at VDD = +5.0V (MAX5200/MAX5201) and at VDD = +3.0V (MAX5202/MAX5203). INL and DNL are guaranteed for outputs between 0.5V to (VDD - 0.5V). Guaranteed monotonic. VREF = 2.5V (MAX5200/MAX5201) and VREF = 1.5V (MAX5202/MAX5203). RL = , digital inputs are at VDD or DGND.
_______________________________________________________________________________________
5
Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in MAX MAX5200-MAX5203
Typical Operating Characteristics
(VDD = +5V, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. CODE
MAX5200 toc01 MAX5200 toc02
SUPPLY CURRENT vs. TEMPERATURE
1.0 16 12 8
DIFFERENTIAL NONLINEARITY vs. CODE
0.75 0.50 DNL (LSB) 0.25 0 -0.25 -0.50 -0.75 -1.00
MAX5200 toc03
1.00
0.9 SUPPLY CURRENT (mA)
INL (LSB) -40 -20 0 25 50 75 85
0.8
4 0 -4 -8 -12
0.7
0.6
0.5 TEMPERATURE (C)
-16 0 10,000 20,000 30,000 40,000 50,000 60,000 70,000 DAC CODE
0
10,000 20,000 30,000 40,000 50,000 60,000 70,000 DAC CODE
GAIN ERROR vs. TEMPERATURE
MAX5200 toc04
OFFSET ERROR vs. TEMPERATURE
0.30 OFFSET ERROR (mV) 0.20 0.10 0 -0.10 -0.20 -0.30 -0.40
MAX5200 toc05
HALF-SCALE OUTPUT SETTLING TIME (CODE FROM 4000H TO C000H)
MAX5200 toc06a
0.10 0.08 0.06 GAIN ERROR (%FSR) 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 -40 -20 0 20 40 60 80 TEMPERATURE (C)
0.40
LARGE SIGNAL (1V/div)
OUT 1V/div
SMALL SIGNAL (1mV/div) RLOAD = 10k CLOAD = 250pF -40 -20 0 20 40 60 80 40s/div
OUT 1mV/div
TEMPERATURE (C)
HALF-SCALE OUTPUT SETTLING TIME (CODE FROM C000H TO 4000H)
MAX5200 toc06b
OUTPUT NOISE DENSITY vs. FREQUENCY
DAC CODE = 8400 HEX 600 500 400 300 200 100 0
MAX5200 toc07
700 OUT 1V/div VOLTAGE NOISE DENSITY (nV/Hz)
LARGE SIGNAL (1V/div)
RLOAD = 10k CLOAD = 250pF 40s/div
SMALL SIGNAL (1mV/div)
OUT 1mV/div
100
1k
10k
100k
FREQUENCY (Hz)
6
_______________________________________________________________________________________
Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in MAX
Typical Operating Characteristics (continued)
(VDD = +5V, TA = +25C, unless otherwise noted.)
MAJOR-CARRY OUTPUT GLITCH (CODE FROM 8000H TO 7FFFH)
MAX5200 toc09
MAX5200 toc10
MAX5200-MAX5203
SOURCE-CURRENT CAPABILITY
4.0 CODE = FFFF HEX 3.5 OUTPUT VOLTAGE (V) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 10 20 30 40 SOURCE CURRENT (mA) CODE = 8000 HEX CODE = C000 HEX
MAX5200 toc08
SINK-CURRENT CAPABILITY
4.5 4.0 3.5 OUTPUT VOLTAGE (V) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 3 6 9 12 15 CODE = 0000 HEX CODE = 4000 HEX
4.5
OUT (AC-COUPLED, 5mV/div)
1s/div
SINK CURRENT (mA)
MAJOR-CARRY OUTPUT GLITCH (CODE FROM 7FFFH TO 8000H)
MAX5200 toc11
SHUTDOWN CURRENT vs. TEMPERATURE
0.75 SHUTDOWN CURRENT (A) 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 -40 -20 0 20 40 60 80
MAX5200 toc12
1.00
OUT (AC-COUPLED, 5mV/div)
1s/div
TEMPERATURE (C)
_______________________________________________________________________________________
7
Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in MAX MAX5200-MAX5203
Pin Description
PIN 1 NAME CLR FUNCTION Reset DAC Active-Low Input. Pull CLR low to reset the DAC output to midscale output (8000 hex) for MAX5200/MAX5202 and to zero-scale output (0000 hex) for MAX5201/MAX5203. For normal operation, connect CLR to VDD. Reference Voltage Output. Provides a +2.5V (MAX5200/MAX5201) or +1.5V (MAX5202/MAX5203) nominal output. For improved noise performance, bypass with a minimum 0.1F capacitor to AGND. Analog Ground Positive Supply Voltage. Bypass VDD to AGND with a 10F capacitor in parallel with a 0.1F capacitor. DAC Output Voltage Active-Low Chip-Select Input Load DAC Input Serial Data Input Serial Clock Input. Duty cycle must be 40% to 60%. Digital Ground
REF VDD
2 3 4 5 6 7 8 9 10
REF AGND VDD OUT CS LDAC DIN SCLK DGND
Detailed Description
The MAX5200-MAX5203 serial 16-bit, voltage-output DACs are easily configured with a 3-wire serial interface. These devices offer full 16-bit performance with less than 20LSB integral linearity error and less than 1LSB differential linearity error, thus ensuring monotonic performance. Serial data transfer minimizes the number of package pins required. The MAX5200- MAX5203 include control-logic circuitry, a 16-bit data-in shift register, and a DAC register. In addition, these devices employ a precision-bandgap reference and trimmed internal resistors to produce a gain of 2V/V, maximizing the output voltage swing. The MAX5200-MAX5203 output is buffered and the fullscale output voltage is 2 VREF. The MAX5200-MAX5203 feature a hardware reset input (CLR) that, when pulled low, clears the DAC output to zero code 0000H (MAX5201/MAX5203) or resets the DAC output to midscale code 8000 hex (MAX5200/ MAX5202). For normal operation, connect CLR to VDD.
BANDGAP REF
MAX5200- MAX5203 16-BIT DAC OUT
CLR
CS SCLK DIN LDAC CONTROL LOGIC
16-BIT DATA LATCH
SERIAL INPUT REGISTER
AGND
DGND
Figure 1. MAX5200-MAX5203 Simplified Functional Diagram
Digital Interface
The MAX5200-MAX5203 digital interface is a standard 3-wire connection compatible with SPI/QSPI/ MICROWIRE and most DSP interfaces. All of the digital input pins (CS, SCLK, DIN, CLR, and LDAC) are TTL compatible. SCLK can accept clock frequencies as high as 10MHz for a +5V supply and 10MHz for a +3V or +3.3V supply. One of two methods can be used when interfacing and updating the MAX5200-MAX5203. The first requires three digital inputs: CS, DIN, and SCLK (Figure 2). The active-low chip-select input (CS) enables the serial
Internal Reference
The MAX5200/MAX5201 (+5V supply) include an internal reference of 2.5V while the MAX5202/MAX5203 (+3V supply) include an internal reference of 1.5V. The DAC output range is from 0 to 2 VREF. Do not drive external circuitry from this reference. To improve DAC output noise performance, bypass with a low leakage 0.1F minimum capacitor to AGND.
8
_______________________________________________________________________________________
Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in MAX MAX5200-MAX5203
tCP tCH SCLK tCL
tCSS CS tCS0 tCSWH DIN NOTE: LDAC IS LOGIC LOW. D15 tDS
tCS1 tDH tCSH
D14
D0
Figure 2. 3-Wire Interface Timing Diagram
data loading at the data input (DIN). Pull CS low and clock in each bit of the 16-bit digital word on the rising edge of the serial clock (SCLK). Two 8-bit bytes can be used, and do not require any additional time between them. Pulling CS high after loading the 16-bit word transfers that code into the DAC register and then updates the output. If CS is not kept low during the entire loading of the 16-bit word, data is corrupted. In this case, a new 16-bit word must be loaded. LDAC must be kept low at all times for the above instructions. An alternate method of interfacing and updating the MAX5200-MAX5203 can be done with a fourth digital input, the active-low load DAC (LDAC). LDAC allows the output to update asynchronously after CS goes high. It is useful when updating multiple MAX5200- MAX5203s synchronously when sharing a single LDAC and CS line. LDAC must be kept high at all times during the data-loading sequence and must only be asserted when CS is high. Asserting LDAC when CS is low can cause corrupted data. To operate the MAX5200-MAX5203 using LDAC, pull LDAC high, pull CS low, load the 16-bit word as described in the previous paragraph, and pull CS high again. Following these commands, the DAC output only updates when LDAC is asserted low (Figure 3).
Shutdown Mode
The low-power shutdown mode reduces supply current to typically 1A and a maximum of 10A. Shutdown mode is not activated through command words, as is common among D/A converters. These devices require careful manipulation of CS and SCLK (Figure 4). Shutting Down To shut down the MAX5200-MAX5203, change the state of SCLK (either a high to low or low to high transition can be used) and pulse two falling CS edges. In order to keep the device in shutdown mode, SCLK must not change state. SCLK must remain in the state it is in after the two CS pulses. Waking Up There are two methods to wake up the MAX5200- MAX5203. Pulse one falling CS edge or transition SCLK. It takes 50s typically from the CS falling edge or SCLK transition for the DAC to return to normal operation.
Power-On Reset
The MAX5200-MAX5203 have a power-on reset circuit to set the DAC's output to a known state when VDD is first applied. The MAX5200/MAX5202 reset to midscale (code 8000 hex) upon power-up. The MAX5201/MAX5203 reset to zero scale (code 0000 hex) upon power-up. This ensures that unwanted output voltages do not occur immediately following a system power-up, such as a loss of power. It is required to apply VDD first before any other inputs (DIN, SCLK, CLR, LDAC, and CS).
_______________________________________________________________________________________
9
Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in MAX MAX5200-MAX5203
tCP tCH SCLK tCL
tCSS CS tCS0 tCSWH DIN D15 tDS
tCS1 tDH tCSH
D14
D0 tLDACS tLDAC
LDAC
Figure 3. 4-Wire Interface Timing Diagram
tCS0L SCLK
SHUTDOWN
WAKE-UP
CS
tCSWL
tCSWH
A. WAKING UP USING A THIRD FALLING EDGE ON CS.
tCS0L SCLK
SHUTDOWN
WAKE-UP
CS
tCSWL
tCSWH
B. WAKING UP USING A TRANSITION ON SCLK.
Figure 4. Shutdown Timing
Applications Information
Power-Supply and Bypassing Considerations
Bypass the power supply with a 10F capacitor in parallel with a 0.1F capacitor to AGND. Minimize lead lengths to reduce lead inductance. If noise becomes an issue, use shielding and/or ferrite beads to increase isolation.
Output Buffer
The MAX5200-MAX5203 include low-offset, low-noise buffers enabling the output to source 15mA or sink 5mA. The output buffer operates at a slew rate of 0.6V/s. With a 1/4 FS to 3/4 FS output transition, the buffer output typically settles to 1 LSB in less than 25s. The MAX5200-MAX5203 output buffers provide a low 0.2 typical output impedance. The MAX5200- MAX5203 buffer amplifiers typically produce 175nV/Hz noise at 10kHz.
10
______________________________________________________________________________________
Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in MAX MAX5200-MAX5203
VDD 10F
0.1F MC68XXXX PCS0 MOSI SCLK CLR CS DIN SCLK LDAC MAX5200- MAX5203 DGND AGND REF OUT
MAX400
+5V BIPOLAR OUT
(VREF)
-5V
Figure 5. MAX5200-MAX5203 Typical Operating Circuit--Bipolar Output
Table 1. Bipolar Code Table
DAC LATCH CONTENTS MSB LSB 1111 1111 1111 1111 1000 0000 0000 0001 1000 0000 0000 0000 0111 1111 1111 1111 0000 0000 0000 0000 ANALOG OUTPUT, VOUT +VREF x (32,767 / 32,768) +VREF x (1 / 32,768) 0V -VREF x (1 / 32,768) -VREF x (32,768 / 32,768)
Layout Considerations
Digital and AC transient signals coupling to AGND can create noise at the output. Connect AGND to the highest quality ground available. Use proper grounding techniques, such as a multilayer board with a lowinductance ground plane. Wire-wrapped boards and sockets are not recommended. For optimum system performance, use printed circuit (PC) boards with separate analog and digital ground planes. Connect the two ground planes together at the low-impedance power-supply source. Connect DGND and AGND pins together at the IC. The best ground connection is achieved by connecting the DAC's DGND and AGND together, and then connecting that point to the system analog ground plane. If the DAC's DGND is connected to the system digital ground, digital noise can get through the DAC's analog portion.
Bipolar Configuration
The MAX5200-MAX5203 are designed for unipolar operation, but can be used in bipolar applications with an external amplifier and resistors. Figure 5 shows the MAX5200-MAX5203 configured for bipolar operation. The op amp is set for unity gain. Table 1 lists the offset binary code for this circuit. The output voltage range is VREF.
Chip Information
TRANSISTOR COUNT: 8764 PROCESS: BiCMOS
______________________________________________________________________________________
11
Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in MAX MAX5200-MAX5203
Selector Guide
PART MAX5200AEUB MAX5200ACUB MAX5200BEUB MAX5201AEUB MAX5201ACUB MAX5201BEUB MAX5202AEUB MAX5202ACUB MAX5202BEUB MAX5203AEUB MAX5203ACUB MAX5203BEUB INTEGRAL NONLINEARITY (LSB, MAX) 20 20 40 20 20 40 20 20 40 20 20 40 SUPPLY VOLTAGE RANGE (V) 4.75 to 5.25 4.75 to 5.25 4.75 to 5.25 4.75 to 5.25 4.75 to 5.25 4.75 to 5.25 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 2.7 to 3.6 REFERENCE INPUT RANGE (V) 2.5 2.5 2.5 2.5 2.5 2.5 1.5 1.5 1.5 1.5 1.5 1.5 POWER-ON-RESET VALUE Midscale Midscale Midscale Zero Zero Zero Midscale Midscale Midscale Zero Zero Zero
12
______________________________________________________________________________________
Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in MAX
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
10LUMAX.EPS
MAX5200-MAX5203
e
10
4X S
10
INCHES MAX DIM MIN 0.043 A 0.006 A1 0.002 A2 0.030 0.037 D1 0.116 0.120 D2 0.114 0.118 E1 0.116 0.120 E2 0.114 0.118 H 0.187 0.199 L 0.0157 0.0275 L1 0.037 REF b 0.007 0.0106 e 0.0197 BSC c 0.0035 0.0078 0.0196 REF S 0 6
MILLIMETERS MAX MIN 1.10 0.05 0.15 0.75 0.95 2.95 3.05 2.89 3.00 2.95 3.05 2.89 3.00 4.75 5.05 0.40 0.70 0.940 REF 0.177 0.270 0.500 BSC 0.090 0.200 0.498 REF 0 6
H y 0.500.1 0.60.1
1
1
0.60.1
TOP VIEW
BOTTOM VIEW
D2 GAGE PLANE A2 A b A1 D1
E2
c
E1 L1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 10L uMAX/uSOP
APPROVAL DOCUMENT CONTROL NO. REV.
21-0061
1 1
I
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

▲Up To Search▲

Price & Availability of MAX5200

	To Download MAX5200 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .